Issue No.06 - November/December (2000 vol.20)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.888701
Power dissipation limits have emerged as a major constraint in the design of microprocessors. This is true not only at the low end, where cost and battery life are the primary drivers, but also now at the midrange and high-end system (server) level. Thus, the ability to estimate power consumption at the high level, during the early-stage definition and trade-off studies is a key new methodology enhancement sought by design and performance architects. We first review the fundamentals in terms of power estimation and power-performance trade-offs at the microarchitecture level. We then discuss the opportunities of saving power that can be exposed via microarchitecture-level modeling. In particular, the potential savings that can be effected through straightforward clock-gating techniques is cited as an example. We also describe some future ideas and trends in power-efficient processor design. Examples of how microarchitectural observations can be used toward power-saving circuit design optimizations are described. The design and modeling challenges are in the context of work in progress within IBM Research. This research is in support of future, high-end processor development within IBM.
David M. Brooks, Pradip Bose, Stanley E. Schuster, Hans Jacobson, Prabhakar N. Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor Zyuban, Manish Gupta, Peter W. Cook, "Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors", IEEE Micro, vol.20, no. 6, pp. 26-44, November/December 2000, doi:10.1109/40.888701