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The IA-64 architecture was designed to allow the compiler to exploit a high level of instruction-level parallelism. Predication, control and data speculation, register rotation, loop branches, and a large register file are powerful features that the compiler can utilize to generate high-performance code. The task of making the best use of these features falls primarily upon the code-generation phase of the compiler. This article describes the important phases of the code generator of Intel's IA-64 production compiler. Specifically, it describes the predicator, global code scheduler, software pipeliner, and register allocator.

J. Pierce et al., "The Intel IA-64 Compiler Code Generator," in IEEE Micro, vol. 20, no. , pp. 44-53, 2000.
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