Issue No. 05 - September/October (2000 vol. 20)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.877949
The IA-64 architecture was designed to allow the compiler to exploit a high level of instruction-level parallelism. Predication, control and data speculation, register rotation, loop branches, and a large register file are powerful features that the compiler can utilize to generate high-performance code. The task of making the best use of these features falls primarily upon the code-generation phase of the compiler. This article describes the important phases of the code generator of Intel's IA-64 production compiler. Specifically, it describes the predicator, global code scheduler, software pipeliner, and register allocator.
Jay Bharadwaj, William Y. Chen, Weihaw Chuang, Gerolf Hoflehner, Kishore Menezes, Kalyan Muthukumar, Jim Pierce, "The Intel IA-64 Compiler Code Generator", IEEE Micro, vol. 20, no. , pp. 44-53, September/October 2000, doi:10.1109/40.877949