Issue No. 02 - March/April (2000 vol. 20)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.848474
Chip multiprocessors offer an economical, scalable architecture for future microprocessors. Thread-level speculation support allows them to speed up past software.
K. Olukotun, M. K. Prabhu, M. Chen, L. Hammond, B. A. Hubbert and M. Siu, "The Stanford Hydra CMP," in IEEE Micro, vol. 20, no. , pp. 71-84, 2000.