Issue No. 01 - January/February (2000 vol. 20)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.820050
We evaluate a series of three progressively more aggressive routing-table cache designs and demonstrate that the incorporation of hardware caches into Internet processors, combined with efficient caching algorithms can significantly improve overall packet forwarding performance.
Prashant Pradhan, Tzi-cker Chiueh, "Cache Memory Design for Internet Processors", IEEE Micro, vol. 20, no. , pp. 28-33, January/February 2000, doi:10.1109/40.820050