Issue No. 01 - January/February (2000 vol. 20)
Interconnecting communicating entities is one of the fundamental problems in computer science and engineering. Interconnection problems occur at various levels—between gates in a chip, between chips on a module or board, between boards across a backplane, and among autonomous computer systems that may span large geographical areas. The complexity of interconnections often has a profound influence on the cost, performance, and reliability of the resulting system.
This special issue of IEEE Micro features six articles on the topic of interconnection and networking, drawn from the papers presented at the Seventh IEEE Hot Interconnects Symposium held at Stanford University in August 1999. The annual Hot Interconnects is held as a companion to the IEEE Hot Chips Symposium. Hot Interconnects covers a large spectrum of interconnect topics, from circuit-level technology to network architectures and protocols. The organizers particularly direct the sessions at new, exciting product and technology innovations in these areas. This year's symposium featured presentations on network switching and routing, optical interconnects and networking, network-attached storage systems, system-level I/O interconnect technologies, and home networks. The six articles included here represent a cross section of the 22 papers presented at the symposium.
The articles address interconnection and networking problems at various levels and in different contexts. The first article, "Architectural Considerations for CPU and Network Interface Integration," discusses the design of efficient network interfaces. This problem is becoming increasingly important because of the range of devices that are being connected to the Internet. Achieving the desired performance at a low cost requires the integration of processing and interface functions on the same chip. The authors propose an architecture that integrates network interface functions with a processor and evaluates its performance in two example applications.
A critical function that needs to be performed within every packet switch or router is address lookup. This function is responsible for determining the outgoing link to forward an incoming packet, based on address information contained within the packet. When forwarding occurs at the IP (Internet Protocol) layer, the operation is more complex than a flat lookup of an address to yield the forwarding information. The routing table in an IP router or switch is usually organized as a set of address prefixes, and the function of the lookup algorithm is to determine the longest prefix in the table that matches the destination address of the incoming packet. The recent literature has proposed many algorithms for the efficient determination of such longest prefix matches. The "Cache Memory Design for Internet Processors" article proposes the caching of address ranges in the lookup table as a solution to the problem and evaluates the trade-offs involved.
Packet classification is another important problem in the design of routers and switches, where one or more header fields of an incoming packet are matched against a set of rules to determine its class. Packet classification may be necessary for several reasons (service differentiation, service guarantee provisions, policy enforcement, congestion control, and load balancing). This function is becoming increasingly important because of the need for supporting multiple types of traffic in packet networks. Because of the need to classify packets along multiple dimensions, the problem is computationally demanding. However, the recent literature has proposed a number of algorithms to provide this function in switches and routers. These algorithms make trade-offs among the classification time, size of the data structure maintained by the algorithm, and time needed for preprocessing the rule database into the internal data structures.
In "Classifying Packets With Hierarchical Intelligent Cuttings," the authors observe that deterministic algorithms to solve the general packet classification problem can be too expensive for large rule bases, and propose heuristic algorithms as an attractive alternative. Their approach is to divide the space in each dimension recursively into intervals and organize the rules that fall into each interval as the nodes in a tree. The partitioning is done such that the number of rules represented by each node in the tree is within a set limit. This can result in an efficient search tree for a given set of rules, making the classification fast. However, the drawback is the long preprocessing time to generate the data structure. The approach is attractive when the rules do not change frequently, so that the data structure will not need to be updated often.
Traffic scheduling is yet another function supported by current-generation switches and routers. The function of a traffic-scheduling algorithm is to determine the relative priorities among the packets that are competing for transmission on an outgoing link. These algorithms are necessary for providing bandwidth and delay guarantees to packet streams, and for the fair distribution of resources in the network. The authors of "A Scheduler ASIC for a Programmable Packet Switch" describe the implementation of a scheduling algorithm in a chip designed at the University of Toronto.
The last two articles deal with I/O interconnection. The first, "Authenticating Network-Attached Storage," concerns the attachment of a storage device directly to a computer network such as a LAN (local-area network). This eliminates the need for specialized standards and protocols for I/O interconnection. However, computer networks are much more accessible and much less secure than I/O networks, and require authentication mechanisms to maintain the integrity of the I/O system in an open network environment. The authors propose solutions to this problem.
The final article evaluates the IEEE-1394 serial bus, which is widely used for the interconnection of consumer electronics equipment such as camcorders to personal computers. In "An Empirical Analysis of the IEEE-1394 Serial Bus Protocol," the authors provide insights into the operation of the IEEE-1394 bus protocols from measurements performed on several system configurations, using an analyzer they designed.
Hot Interconnects 8 will meet once again at Stanford University in 2000. For information, visit the symposium Web site at www.hoti.org.
The Hot Interconnects Program Committee and a few other reviewers reviewed all the papers submitted to the symposium, including the articles presented here. We thank them for their efforts. We also thank Daniel Pitt, Hot Interconnects 7 general chair, for the opportunity to serve as program chairs for the symposium.
Anujan Varma is a professor of computer engineering at the University of California, Santa Cruz. Previously, he worked at the IBM Thomas J. Watson Research Center in Yorktown Heights, New York, and has consulted extensively for the networking and semiconductor industries. His current research interests are in high-speed switching and routing hardware, traffic management, optical networks, congestion control and scheduling, and video and audio transport over packet networks. Varma received his PhD in computer engineering from the University of Southern California. He has published over 100 papers in refereed journals and conference proceedings, and holds nine patents. He has received several awards including the National Science Foundation Young Investigator award, the IEEE Darlington award, and a teaching innovation award from the University of California.
Mark Laubach is an independent consultant and a cofounder and past vice president and chief technology officer at Com21 in Milpitas, California. There, he directed the end-to-end systems architecture, protocol design, performance, and technology of CATV broadband access telecommunications products. Earlier, he worked with the Hewlett-Packard Company. Laubach holds a bachelor's degree in electrical engineering and a master's in computer science from the University of Delaware. He is past chair of the IP-over-ATM working group and the author of the RFC1577/2225 Classical IP and ARP Over ATM (IPOA) standard. He has participated in cable TV standards activities (IEEE, IETF, ATM Forum, SCTE, and CableLabs' DOCSIS). He is a senior member of IEEE and a member of the ACM and SCTE (Society of Cable Telecommunications Engineers).