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This reconfiguration method quickly repairs single and multiple faults in FPGAs with low delay overhead. Experiments showed 100% successful reconfiguration with single faults. We give a comprehensive approach for reconfiguring one-time programmable (OTP) field-programmable gate arrays (FPGAs). The objective of the approach is fourfold: (1) no design-for-reconfigurability modifications to the FPGA are made, (2) no alterations should be required of the product design, (3) modest change in the delay of the reconfigured circuit, and (4) rapid calculation of the amended configuration so that the additional programming can be accomplished during production programming. Delay-optimal reconfiguration is NP complete. So we use greedy algorithms to provide rapid, but sub-optimal solutions. This is suitable for application to an assembly line in which chips are programmed and tested online. We give reconfiguration algorithms to handle failures in programmable routing resources, as well as for programmable logic function resources. To compute the reconfiguration, we only need to make calls to a detail router, which uses only local routing information and thus is fast. For failed routing resources, calls to the detail router are linear in the number of faults. For failed logic resources, calls to the detail router are quadratic in the worst case and linear in the average case. For logic resource faults, reconfiguration is guaranteed if the routing channels have a sufficient number of spare tracks in the channels provided that any multiple faults do not conflict. For routing resource faults, we consider a model of correlated faults in which clusters of faults hit blocks of programmable routing resources. We show that the repairability depends strongly on the total number of faults and weakly on the number of fault clusters. For experimentation, we use a generic OTP FPGA model and a generic detail router provided by the University of Toronto. Since the availability of spare tracks in the routing channels is a key factor, we investigate biasing the routing software more strongly toward balancing the spare channel capacity. This generally achieves an improvement in the worst case spare channel capacity.
Xiao-Tao Chen, Fred J. Meyer, Wenyi Feng, Jun Zhao, Fabrizio Lombardi, "Reconfiguring One-Time Programmable FPGAs", IEEE Micro, vol. 19, no. , pp. 53-63, November/December 1999, doi:10.1109/40.809378
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