Issue No. 04 - July/August (1999 vol. 19)
Today, we are in an era of expanding multimedia demand. Our information-oriented society depends on a network infrastructure based on personal mobile computing and communications devices. These devices are the basis for handheld PCs, portables (laptops), cellular phones, digital cameras, video games, and pagers. 1 To be effective, the processor in such a device must consume very low power. Embedded processors are now being fabricated to include various systems components (memory, signal processors, and so on); they will be pervasive in many mobile multimedia computing applications.
In Japan, we call a system-on-a-chip a System LSI. In System LSI, an embedded processor is regarded as a collection of IP (intellectual property). 2 This System LSI requires the integration of IP obtained from multiple sources. To realize this, we face many challenges and complicated issues such as interfacing, simulation, test, and verification. Although these issues already exist in today's embedded processors at the board level, the System LSI creates a spectrum of new problems. For example, signals are not easily accessible inside a chip, and accurate simulation of hundreds of millions of gates is very difficult.
There are two main approaches to minimizing power in high-performance multimedia processors. One lowers the supply voltage and reduces the device capacitance in chips. 3 The other reduces power consumption with a careful selection or creation of instruction sets, depending on the applications. 4 On the other hand, workstation and server applications require high-speed, high-end microprocessors. 5 Their high clock rate requires commensurate power dissipation, causing thermal problems in these processors. The first two articles in this special issue of IEEE Micro note that power scales as the cube of the frequency. Doubling the frequency can require eight times the power.
Power management of a chip includes minimizing chip power consumption as well as efficiently conducting heat away from the processor with effective package designs. Clearly, a symposium series dedicated to understanding power management is necessary. As Stanford University's Michael J. Flynn especially emphasizes, "It's time to stop comparing processors by their MHz and start comparing them by their mW or μW."
This issue of IEEE Micro includes a selection of articles based on presentations at the second Cool Chips Symposium held at Kyoto Research Park in Kyoto on 26-27 April 1999.
This Asian-based symposium series attracts academic and industrial processor engineers and architects. In spring 1997, Kevin Rudd of Stanford proposed an Asian Hot Chips in Japan, motivated in part by a beautiful moment at Japan's Akyu hot springs. At that time, snow was falling into the steaming outdoor hot springs. This scene seemed to be a metaphor for the heat management problem of modern microprocessors resulting from the computations that are "steaming" through: The environment must somehow cool the processor. Later, Flynn suggested the name Cool Chips, again based on the environmental concerns 6 for both general-purpose microprocessors and, more importantly, embedded processors. 7
The first Cool Chips met in Tokyo as a one-day symposium and consisted of only invited speakers. The symposium's objectives were to present the architecture, design, and implementation of chips, emphasizing the constraints of cost, power, and performance. The participants found the symposium very helpful in understanding recent developments in chip technology.
This year's two-day Cool Chips II included presentations by keynoter Michael J. Flynn of Stanford University and invited speakers from KAIST (Korea Advanced Institute of Science and Technology), ATR (Human Information Processing Research Laboratories)/NTT, Texas Instruments, Intel, and Stanford University. In addition, Cool Chips II offered contributed presentations from NEC, IBM Japan, NTT, Mitubishi Electric, KAIST, ETL (Electrotechnical Laboratory), Keio University, Fujitsu Laboratories, Fujitsu Microelectronics Israel, SandCraft, Rohm, Motorola, and Hitachi Semiconductor America. It included presentations on workstation processors, low-power processor implementations, media processors, embedded processors, and others. Further, participants from Nagoya University, Oki, Samsung Semiconductor, Soongsil University, Motorola, Toukai University, and ARM joined a poster session later in the symposium.
At Cool Chips II, the papers reflected the interest in low-power and high-speed chips. The articles selected for this special issue of IEEE Micro represent these interests. The first article, "Deep-Submicron Microprocessor Design Issues" by Flynn and colleagues, explains the basic deep-submicron design methodology for microprocessors. In the VLSI and the computer architecture technologies there are many trade-offs that present fundamental and new opportunities for optimizing designs.
"Design Challenges of Technology Scaling" by Borkar evaluates trends in process technology and microprocessors against scaling theory. "Micro-RISC Architecture for the Wireless Market" by Gonzales discusses the low-power features of the embedded M•CORE architecture and describes a dual-processor solution for a TDMA baseband transceiver.
"The D30V/MPEG Multimedia Processor" by Takata and colleagues describes how to achieve real-time MPEG-2 decoding and DVC (digital videocassette) encoding/decoding. "High-Performance RISC Microprocessors" by Choquette et al. describes the architectural philosophy behind the development of a line of high-performance RISC microprocessors. Finally, "SuperENC: MPEG-2 Video Encoder" by Ikeda et al., presents an architecture for a single-chip MPEG-2 video encoder with scalability for HDTV and demonstrates its flexibility and usefulness.
I trust that you will find this special issue devoted to Cool Chips II to be helpful as well as interesting. Send me your comments and questions; I look forward to receiving your feedback for Cool Chips III, which will focus on more concrete designs of cool chips.
Tadao Nakamura is a professor in the Department of Computer and Mathematical Sciences at Tohoku University. His research interests include computer architecture on a chip, supercomputers, and computer graphics. He has also been a visiting professor at Stanford University, where he promotes brain-structured supercomputers in a joint research project with Michael J. Flynn. Nakamura received his PhD from Tohoku University. He has served as chair of the Cool Chips I and II organizing committees and is a Senior Member of the IEEE Computer Society.