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Issue No.03 - May/June (1999 vol.19)
pp: 26-35
This paper presents a new PowerPC-based performance simulation tool that has full-function capability. The new tool fMW is developed from the integration of the functional simulator PSIM and the cycle-accurate performance simulator MW. The two tools work in a tightly coupled fashion to facilitate new simulation capabilities. fMW is capable of: 1) simulating mispredicted path instructions and value prediction techniques; 2) simulating multiple instruction streams of a program; and 3) verifying test sequences for the validation of speculation and recovery mechanisms. The fMW tool is implemented and used in two recent studies. The first study examines the effects mispredicted path instructions have on the instruction cache hierarchy. The second study quantifies the coverage achieved by test sequences for the thorough validation of register renaming and out-of-order execution mechanisms. These studies demonstrate the weaknesses and inaccuracies of previous tools, while illustrating the strengths of the new fMW tool.
Candice Bechem, Jonathan Combs, Noppanunt Utamaphethai, Bryan Black, R.d. Shawn Blanton, John Paul Shen, "An Integrated Functional Performance Simulator", IEEE Micro, vol.19, no. 3, pp. 26-35, May/June 1999, doi:10.1109/40.768499
1. B. Black and JP. Shen, "Calibration of Microprocessor Performance Models," Computer, May 1998, pp. 59-65.
2. P. Bose, "Performance Test Case Generation for Microprocessors," Proc. 16th VLSI Test Symp., IEEE Computer Soc., Los Alamitos, Calif., Apr. 1998, pp. 54-59.
3. P. Bose and S. Surya, "Architectural Timing Verification of CMOS RISC Processors," IBM J. Research and Development, Jan./Mar. 1995, pp. 113-129.
4. D. Burger and T. Austin, "The SimpleScalar Tool Set, Version 2.0," Tech. Report 1342, Univ. of Wisconsin-Madison, 1997.
5. M. Reilly and J. Edmondson, "Performance Simulation of an Alpha Microprocessor," Computer, May 1998, pp. 50-58.
6. T.A. Diep and J.P. Shen, "VMW: A Visualization Based Microarchitecture Workbench," Computer, Dec. 1995, pp. 57-64.
7. A.S. Huang and T.A. Diep, "MW Developer's Guide," CMuART Tech. Report 95-1, ECE Dept., Carnegie Mellon Univ., Pittsburgh, Aug. 1995.
8. M.H. Lipasti, C.B. Wilkerson, and J.P. Shen, "Value Locality and Load Value Prediction," Proc. Seventh Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, ACM Press, New York, 1996, pp. 138-147.
9. M.H. Lipasti and J.P. Shen, "Exceeding the Data-Flow Limit Via Value Prediction," Proc. 29th Ann. ACM/IEEE Int'l Symp. on Microarchitecture, IEEE CS Press, Los Alamitos, Calif., 1996, pp. 226-237.
10. N. Utamaphethai, R.D. Blanton, and J.P. Shen, "Validation of Speculativeand Out-of-Order Execution Microarchitectures," Proc. Microprocessor Test and Verification Workshop (MTV98), Oct. 1998.
11. N. Utamaphethai, R.D. Blanton, and J.P. Shen, "A Buffer-Oriented Methodology for Microarchitecture Validation," J. Electronic Testing: Theory and Application, Special Issues on Microprocessor Test and Verification, to appear Fall 1999.
12. A. Cagney, "PSIM User's Guide," / , Aug. 1996.
13. J. Combs, C. Bechem, and J.P. Shen, "Mispredicted Path Cache Effects," CMuART Tech. Report, ECE Dept., Carnegie Mellon Univ., Jan. 1999.
14. D. Lee et al., "Instruction Cache Fetch Policies for Speculative Execution," Proc. Int'l Symp. Computer Arch., IEEE CS Press, 1995, pp. 357-367.
15. J. Pierce and T. Mudge, "The Effect of Speculative Execution of Cache Performance." Proc. Int'l Parallel Processing Symp., IEEE CS Press, 1994, pp. 172-179.
16. J. Pierce and T. Mudge, "Wrong Path Instruction Prefetching," Tech. Report, Electrical Engineering and Computer Sci. Dept., Univ. of Michigan, Ann Arbor, 1994.
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