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Issue No.03 - May/June (1999 vol.19)
pp: 9-14
The methodology for designing state-of-the-art microprocessors involves modeling at various levels of abstraction. In the pre-synthesis phase, this can range from early-stage (microarchitectural) performance-only models to final-stage, detailed register-transfer-level (RTL) models. Hierarchical modeling requires the use of an elaborate validation methodology to ensure inter- and intra-level model integrity. The RTL model, often coded in a hardware description language (e.g. Verilog or VHDL) captures the logical behavior of the entire chip: both in terms of function and cycle-by-cycle pipeline flow timing. It is this model that is subjected to simulation-based architectural validation prior to actual "tape-out" of the processor. The validated RTL specification is used as the source reference model for synthesizing the gate- and circuit-level descriptions of the processor.
Pradip Bose, Thomas M. Conte, Todd M. Austin, "Guest Editors' Introduction: Challenges in Processor Modeling and Validation", IEEE Micro, vol.19, no. 3, pp. 9-14, May/June 1999, doi:10.1109/MM.1999.768495
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