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Issue No. 01 - January/February (1999 vol. 19)
ISSN: 0272-1732
pp: 68-79
This article presents a fast digital Fuzzy Processor that has already been designed and realized in 0.7-(m digital CMOS technology obtained by European Silicon Structure (ES2) silicon foundry. It processes four 7-bit input variables and carries out one 7-bit output one. It may be synchronized up to a 50-MHz clock signal for an estimated power consumption of nearly 1300 mW. Moreover the rate of this chip varies from 80 ns to 320 ns depending on the number of input variables. The innovative idea is the no-time consuming methodology for selecting the fuzzy active rules. This is done by a parallel-pipeline architecture described in details. In the paper are summarized the Fuzzy Processor future implementations for High Energy Physics Experiments (HEPE). In addition, the architecture is explained with layout and data flow simulation pictures. Moreover the fuzzy logic methodologies which have been adopted are justified in terms of hardware implementation feasibility and speed requirements.
Fuzzy processors, design methodology, fuzzy rules, parallel-pipeline architecture

E. Gandolfi and A. Gabrielli, "A Fast Digital Fuzzy Processor," in IEEE Micro, vol. 19, no. , pp. 68-79, 1999.
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