Issue No. 05 - September/October (1998 vol. 18)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.735942
A new approach to enhance the reliability of embedded processor-based systems is presented. It was developed for applications with high-reliability demands under heavy cost-constraints. The concept is a minimized duplication of processor macro-components in programmable logic devices in accordance with the application of the embedded system. This concept is described in detail with the design flow of the processor control structure as an example. We show that the hardware overhead and the costs of classical fault-tolerant techniques like triple-modular redundant (TMR) component implementation can be reduced significantly. Furthermore, we show the possibilities and limitations of programmable logic devices used in this approach.
Fault tolerance, embedded systems, PLDs
M. Pflanz and H. T. Vierhaus, "Generating Reliable Embedded Processors," in IEEE Micro, vol. 18, no. , pp. 33-41, 1998.