, Swiss Federal Institute of Technology, Zurich
Pages: pp. 7-9
Packaging in computer and communication systems has become increasingly significant in the last few years. In particular, the position of packaging within product development is clearly changing toward a matched and concurrent design with ICs. A revolution in the relationship between front-end (IC) and back-end (package) design has already started.
The past three decades of electronic product design have been characterized by a plainly defined allocation of functionality within the design chain. In that chain, IC design remains widely independent of the final application. On the other hand, packaging and assembly must adapt IC functionality to the specific product application environment. Interaction in the design phase in this function hierarchy is rather low. Making use of the steady progress in semiconductor technology, IC designers strive to concentrate the system functionality in the IC, whereas packaging and assembly must provide cost-effective solutions for die protection, signal interconnection, power supply, and heat dissipation.
This independent and serial design flow of ICs and packaging shows one main advantage: due to clear interfaces, an individual optimization concerning performance or cost within each design level is possible. This work sharing is based on the fundamental assumption that packaging and board assembly don't degrade IC and system performance.
However, work sharing also increasingly limits our use of the exploding IC performance at the system level. Mainly, the speed and memory bandwidth in high-performance computing systems, as well as the demand for the lowest power consumption and ultradense packaging in mobile communications, will dissolve the classical hierarchy between ICs and packaging.
Consider futuristic applications such as wristwatch-size satellite phones or wearable computing modules distributed within our clothes. In such applications, the fusion of ICs with their applications implies codesign on the IC and the system levels. Our definition of codesign—exploiting the synergism of ICs and packaging through their concurrent and matched design to meet system-level objectives—emphasizes three characteristic features. They are system orientation, distribution of the functionality between IC and packaging, and a comprehensive design flow.
At the moment, off-chip routing and the integration of passive components are the most forward-looking codesign concepts. The lower wire resistance and capacitance of interconnection lines on a board or MCM (multichip module) reduces clock delay, power consumption, and chip area at the system level. This occurs when the routing of (and therefore the functionality of) the complete system is distributed between on- and off-chip interconnect levels. Passive components integrated beneath the ICs in the substrate (single-chip packages or MCMs) open up new architectures for RF circuits and the merger of analog and digital systems. In the digital domain, EMI (electromagnetic interference) requirements, simultaneous switching noise restrictions, signal integrity, and cost reduction by less external discrete components also demand integrated components.
What are the relevant barriers that prevent the exploitation of the obvious codesign benefits? In the last three decades, front- and back-end design as well as manufacturing have normally been fostered in different worlds, separated in differently structured companies or even in the same company. Clearly, performance and the highly innovative technology drive front-end design, whereas cost and system requirements drive the back end. These structural differences brought about different design cultures, societies, and education, and thus different design environments and CAD tools. IC designers are mostly circuit and system oriented; physicists are mostly involved in packaging.
System and module designers can exploit the added value of codesign. The crucial point is the possible benefit for IC manufacturers should they have to adapt their products to specialized packaging with an increased dependence from the system manufacturer. The reserved introduction of bare dies illustrates these divergent interests. Therefore it is obvious that codesign will first be introduced on the module level where the improved cost/performance ratio can easily be shared between the IC and system houses. To meet the aggressive cost/performance requirements of future electronic systems, alliances between the IC and packaging worlds will become more and more unavoidable.
This spring, two international workshops marked the beginning of this emerging technology: the IPDI-98 (IEEE Symposium on IC/Package Design Integration, Santa Cruz, Calif., 2-3 Feb. 1998) and the CPD98 (IEEE International Workshop on Chip-Package Co-Design, ETH, Zurich, 24-26 Mar. 1998). Their topics spanned package foundry infrastructure, chip-package/MCM partitioning, power system design, and cost evaluation. These workshops will continue, corresponding to the growing interest in this interdisciplinary codesign approach.
For this special issue, I've selected six articles (partly from the two workshops just mentioned), which illustrate the broad spectrum of codesign. They address concepts as well as enabling technologies for codesign.
To distribute the system functionality between ICs and packages/MCMs, high-density substrates for PWBs (printed wiring boards) and MCMs must provide the necessary bandwidth. Happy Holden impressively illustrates the innovative potentials of the well-established PWB technology as the most cost-effective solution for high-density interconnection.
The step from planar to three-dimensional packaging of electronic systems remains a challenge for the integration technology. On the other hand, 3D integration is indispensable for further miniaturization, but it requires a new quality of teamwork between IC design, fabrication, and assembly. Mitsumasa Koyanagi explains the status of 3D integration on the basis of an advanced process flow he and his group developed.
The transmission of high-speed signals between different package levels is increasingly becoming the bottleneck in fast digital systems. From the perspective of an RF designer, Jenshan Lin discusses the challenges of multi-GHz clock frequencies in smaller and smaller system environments. Evan Davidson evaluates the crucial conditions of the thrilling race between system-on-a-chip and tiled-silicon solutions for future advanced computing systems.
Etienne Hirt and his colleagues investigate the impact of memory bandwidth provided by area I/O. A case study for a Pentium-class system indicates the significant performance gain achieved when exploiting the matched IC-packaging approach.
The missing CAD environment is one of the biggest barriers to using codesign technologies. How will we simulate the giant microwave systems that the future GHz-clocked processors will be? Andreas Cangellaris provides insight into a novel class of circuit simulators that use Maxwell's equations instead of Kirchhoff's laws.
Now, I invite you to read the articles and enjoy the excitement of a new era that promises to open up extensive vistas in future electronic design.