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Guest Editors' Introduction: The Bleeding Edge

Randy Rettberg, Sun Microsystems
William J. Dally, Stanford University
David E. , University of California at Berkeley

Pages: pp. 10-11

Interconnection issues increasingly dominate modern digital systems. Interconnects, not logic, determine the area, power, and delay of modern integrated circuits. At the board level, the number and speed of the links that connect chips largely determine system bandwidth. At the enterprise level and globally, interconnections between systems provide the infrastructure that is fueling the exponential growth in the Internet.

As interconnects have increased in importance, the Hot Interconnects Symposium has emerged as the leading forum for the discussion of the nuts and bolts of digital communication technology at many scales and in many venues. This symposium collects papers and presentations on the bleeding edge of interconnection research. The emphasis is on novel ideas and the potential for future impact rather than on polished results.

Hot Interconnects is the premier symposium for low-level chip-to-chip and box-to-box signaling, including signaling technology, router architecture, and implementation issues. It has also heavily influenced the area of emerging cluster interconnects: protocols, network adapters, and software architecture. In recent years the symposium has expanded to examine WAN and LAN technologies and switches and routers for networks as well as technologies for network communications links. More often now, hot new products and breakthrough technologies in the interconnect area debut at the symposium.

The 1997 Hot Interconnects program consisted of 21 superb papers selected by the program committee from a field of very high quality submissions. In this special issue of IEEE Micro we bring you the very best of these presentations.


Signaling technology, the foundation on which all interconnects are built, has changed dramatically in recent years with electrical signaling reaching rates of several gigabits per second (Gbps) and optical signaling experiencing major cost reductions at even higher signaling rates. As these technologies evolve, the boundary between electrical and optical signaling, in terms of distance and signaling rate, continues to shift. Optical signaling, currently restricted to very long data links (100 meters and up), holds the potential to take over shorter-distance box-to-box and even chip-to-chip signaling. Electrical signaling, however, is holding its own with new technologies for transceivers, timing circuits, and equalizers that extend signaling rates into a domain once reserved for optics.

The evolution of both electrical and optical signaling technologies was well represented at Hot Interconnects 1997. This special issue includes two full articles and a short update that collectively give a representative view of this field. Horowitz et al., in "High-Speed Electrical Signaling: Overview and Limitations," which is based on Horowitz's keynote talk at the symposium, examines the limits of electrical signaling. The authors show that new transceiver and timing technology put electrical signaling rates back on a Moore's-law curve. Bit times of a single loaded gate delay (for example, 4 Gbps in 0.5 micron) become easily achievable in standard CMOS technology. At these data rates the frequency-dependent loss of the transmission lines becomes a major limiting factor. In the short update article, "A Tracking Clock Recovery Receiver for 4-Gbps Signaling," Dally and Poulton give an example of this class of electrical signaling system with results from a 4-Gbps system with transmitter equalization. Even with these advances in electrical signaling, optical signaling has fundamental advantages at high bit rates and long distances. In "Packet-Switched Optical Networks," Yu and coauthors highlight the capability of optics by describing a time-domain multiplexed system that provides data rates of 100 Gbps in the context of a system bus.


Representing system-level interconnects is "Starfire: Extending the SMP Envelope" on the current technology in symmetric multiprocessor interconnects. Author Charlesworth shows how to obtain a flat 10-Gbyte/s system bandwidth over 64 processors. He uses conventional 100-Mbps signaling technology while preserving the semantics of a broadcast bus.


In recent years the emergence of workstation clusters connected by fast system-area networks has revolutionized parallel computing. The technology of cluster computing had its roots in academic research projects such as NOW at Berkeley, Shrimp at Princeton, FM at Illinois, and UNET at Cornell. Over the years, Hot Interconnects has followed the evolution of these academic prototypes with papers representing two of the projects in this special issue. Dubnicki et al.'s "Shrimp Project Update: Myrinet Communication" provides additional work resulting from research on a Myrinet-based multicomputer. Chun et al.'s "Virtual Network Transport Protocols for Myrinet" reports on the design and performance of a general-purpose protocol for a system area network. Welsh and von Eicken report on design alternatives for managing address translations in the network interface for user-level communication buffers. Due to space limitations, this report will appear in the March-April issue of IEEE Micro.

After several years of academic research, cluster computing has matured to the point that an industry standard has emerged. At Hot Interconnects 1997, Intel introduced the Virtual Interface Architecture, a joint Microsoft, Intel, and Compaq standard for cluster communications. This standard, which builds on the work of the four academic projects (NOW, Shrimp, FM, UNET), will make cluster computing a mainstream technology by providing a standard target for applications developers. The details of VIA were not publicly available at press time, so we were unable to include the article by Dunning et al. in this special issue. It will appear in the March-April issue of IEEE Micro.

Space limitations prevent us from including many more superb papers that were presented at Hot Interconnects this year. Most of these papers are available on the Web, however, at


By bringing together the best of Hot Interconnects V, this special issue gives you an overview of leading-edge research in interconnection technology. The articles provide a glimpse of a future in which interconnects play an increasingly critical role in information systems and the emerging technologies, from signaling to the protocols that will enable this future.

We hope you find these articles as exciting as we have.

Special Note

Last year's Hot Interconnects, and last year's IEEE Micro special issue, contained Dally and Poulton's "Transmitter Equalization for 4-Gbps Signaling" and Damianakis et al.'s article on the Shrimp project. As is typical in this field, the Dally and Poulton article appeared when the design was completed but before the chips returned. Similarly, the Shrimp article reported on the Paragon-based multicomputer, not on results from the Myrinet system. In the past year, these important projects have achieved significant further results, which we present in the two previously mentioned short update articles.


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About the Authors

Randy Rettberg is a distinguished engineer at Sun Microsystems, Inc., where he works on system interconnect and Internet technologies. Previously, at Apple Computer, he participated in the development of the Quadra AV machines and digital cameras. He is known for his work on the Butterfly Parallel Processors and the Monarch while at Bolt Beranek and Newman, Inc. At BBN as part of the Arpanet development team, he developed the C/30 packet switch and the satellite networks used in the early Internet.
Rettberg received his BS degree in electrical engineering from the Massachusetts Institute of Technology and his MS in physics from the University of Illinois.
William J. Dally is a professor of electrical engineering and computer science at Stanford University, where he leads projects on high-speed signaling, multiprocessor architecture, and graphics architecture. While a professor of electrical engineering and computer science at the Massachusetts Institute of Technology, he and his group built the J-Machine, a fine-grain concurrent computer, and developed technology for interconnection networks including network architecture, high-speed signaling and synchronization methods. He has published over 80 papers in these areas.
Dally received a BS degree in electrical engineering from Virginia Polytechnic Institute, an MS degree in electrical engineering from Stanford University, and the PhD degree in computer science from the Caltech. He is a member of the IEEE and ACM.
David E. Culler's biography and photo appear on p. 63 in this issue.
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