Issue No. 05 - September/October (1997 vol. 17)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.621215
In order to support virtual memory, virtual addresses must be efficiently translated into physical addresses. Traditionally, this dynamic translation has been done in a Translation Lookaside Buffer (TLB) before or in parallel with the cache access, so that the cache is indexed and tagged with physical addresses. However, physical-address caches are either slow or limited in size. To solve this bottleneck, caches can be accessed directly with virtual addresses. Unfortunately, consistency problems add complexity to virtual-address caches. These problems are mostly caused by synonyms and address-mapping changes. In this first part, we introduce the problems and discuss solutions in the context of single-processor systems. In Part 2 of this two-part series, we will address multiprocessor issues.
Caches, microprocessors, uniprocessor architecture, multiprocessor architecture
M. Cekleov and M. Dubois, "Virtual-Address Caches Part 1: Problems and Solutions in Uniprocessors," in IEEE Micro, vol. 17, no. , pp. 64-71, 1997.