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Issue No. 05 - September/October (1997 vol. 17)
ISSN: 0272-1732
pp: 20-27
ABSTRACT
Historically, there have been two different approaches to high performance computing: instruction-level parallelism (ILP) and data-level parallelism (DLP). The ILP paradigm seeks to execute several instructions each cycle by exploring a sequential instruction stream and extracting independent instructions that can be sent to several execution units in parallel. The DLP paradigm, on the other hand, uses vectorization techniques to specify with a single instruction (a vector instruction) a large number of operations to be performed on independent data. A few of these vector instructions running concurrently can provide a large operation parallelism for many consecutive cycles.
INDEX TERMS
Multithreading, parallelism, microarchitecture, high-performance processors
CITATION
Roger Espasa, Mateo Valero, "Exploiting Instruction- and Data-Level Parallelism", IEEE Micro, vol. 17, no. , pp. 20-27, September/October 1997, doi:10.1109/40.621210
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