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Guest Editors' Introduction: Celebrating Chips and Architectures

Winfried Wilcke, HAL Computer Systems
Robert Garner, Sun Microelectronics

Pages: pp. 9-10

In keeping with its reputation, the Hot Chips 8 Symposium held at Stanford University in August 1996 featured details of the newest and most-promising chips and architectures. This issue of IEEE Micro contains five articles from the 28 outstanding talks delivered to a record-size audience of about 900 attendees at Hot Chips 8. We based our final selection of these five articles on the feedback received from conference attendees and the program committee's opinions as to the highest quality presentations and most germane subject material.

Several interesting talks at the symposium discussed new chips for 3D graphics and high-performance multimedia: video, imaging, communications, and audio processing. Representative of those talks is the new joint Talisman architecture and the Chromatics Research Mpact media processor.

Talisman is an optimized approach for efficiently rendering 3D scenes for applications such as video games and animation. Rather than rerendering the display list for each frame from scratch, the designers exploited the fact that objects change little between frames; this led to drastically reduced memory and bandwidth requirements. The architecture also heavily relies on compression to reduce memory requirements.

Mpact can execute a wide variety of multimedia algorithms. The media processor is organized as a VLIW (very long instruction word) processor with many functional units, all interconnected with a large crossbar switch.

Representing state-of-the-art, high-performance RISC processors is the HP 8000 article. To achieve peak execution efficiency, this chip emphasizes the importance of a big instruction reorder buffer and large, two-cycle first-level caches.

The remaining two articles discuss new developments. The first is an in-depth analysis of the challenges and opportunities of integrating CPUs and DRAM onto a single die, called intelligent RAM here.

Next is an article on picoJava, the first microprocessor core designed for optimal execution of Java Virtual Machine code. The pros and cons of a special Java processor have been debated with nearly religious fervor during most of 1996 and became the subject of a heated panel discussion at Hot Chips 8.


We hope you enjoy this selection of articles on the leading-edge hot chips.

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About the Authors

Winfried Wilcke just completed a sabbatical as skipper of a sailboat in the Caribbean. His "real" world experience is in system and processor architecture at IBM and HAL/Fujitsu. At HAL, he was the director of the Architecture Department, which, in close collaboration with Sun, was very involved in the definition of the 64-bit Sparc V9 architecture. Later, he started the HAL Mercury project for a scalable, cache-coherent NUMA parallel system. At IBM Yorktown Heights, Wilcke had managed two large parallel multiprocessor projects, one of which was the research prototype for the IBM SP series of highly scalable processors. Before his involvement in computer design, he worked in nuclear physics at the University of Rochester.
Wilcke received his Diploma and PhD degree in physics from J.W. Goethe University, Germany. He is a member of the American Physical Society and the IEEE.
Robert Garner is director of Java Media Processors, the microprocessor design unit of Sun Microelectronics. Earlier, he comanaged the UltraSparc-I program, holding responsibility for the architecture, logic design, and verification teams. He was the coarchitect of the Sparc architecture and lead designer of the Sun 4/200, the company's first Sparc product. He was also a manager of the SparcCenter 2000 multiprocessor project. At Xerox, he codesigned the Star Professional Workstation and served on the staff at the Palo Alto Research Center.
Garner received his BSE degree from Arizona State University and his MSEE from Stanford University. He is a member of the IEEE and the Computer Society.
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