Issue No. 05 - October (1996 vol. 16)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.540077
The Neural Network Design Group at SGS-Thomson Microelectronics has been working to explore the advantages and limitations of analog computation and neural network architectures. We are investigating 3 large-scale analog VLSI chips, all of which work on problems in image processing. The use of analog computing arrays, because of their efficiency and regularity, have formed the basis of all of our designs, while several different computing modes, including current, charge, and conductance have been explored. Another area in which we have focused is on the use of floating-gate devices for both non-volatile analog storage and computation. This paper shares insights into the lessons we have learned, the results we have achieved and the limitations we have encountered. Particular emphasis is made on two subjects: computational efficiency and equivalent precision of array-based analog computing circuits.
A. H. Kramer, "Array-Based Analog Computation," in IEEE Micro, vol. 16, no. , pp. 20-29, 1996.