Issue No. 02 - April (1996 vol. 16)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.491461
UltraSPARC-I is a general-purpose processor implementing the SPARC V9 64-bit RISC architecture. In addition to supporting this Instruction Set Architecture (ISA), UltraSPARC-I includes over 30 new multimedia instructions (VIS - Visual Instruction Set) that provide the most common operations related to image processing, two- and three-dimensional graphics, video compression/decompression algorithms, etc. The simple in-order execution model implemented on UltraSPARC-I allows a balance between a high clock rate and a relatively wide (four-issue) machine. Microarchitecture features allowing the processor to sustain an execution of four instructions per cycle even in the presence of conditional branches and cache misses are described. The second part of the article focuses on the microarchitecture features that the software can leverage to achieve higher performance, including some of the multimedia features implemented on chip.
Microprocessors, RISC, superscalar, multimedia, VIS, 64-bit
Marc Tremblay, J. Michael O'Connor, "UltraSparc I: A Four-Issue Processor Supporting Multimedia", IEEE Micro, vol. 16, no. , pp. 42-50, April 1996, doi:10.1109/40.491461