Issue No. 02 - April (1996 vol. 16)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.491460
The Mips R10000 is a dynamic superscalar microprocessor that implements the 64-bit Mips-4 Instruction Set Architecture. It fetches and decodes four instructions per cycle and dynamically issues them to five fully pipelined low-latency execution units. Instructions can be fetched and executed speculatively beyond branches. Instructions graduate in order upon completion. Although instructions execute out of order, the processor still provides sequential memory consistency and precise exception handling. The R10000 is designed for high performance, even in large real-world applications which have poor memory locality. With speculative execution, it calculates memory addresses and initiates cache refills early. Its hierarchical nonblocking memory system helps hide memory latency with two levels of set-associative, write-back caches.
Microprocessors, superscalar, Mips R10000, cache memory, instruction execution
K. C. Yeager, "The MIPS R10000 Superscalar Microprocessor," in IEEE Micro, vol. 16, no. , pp. 28-40, 1996.