Issue No. 06 - December (1995 vol. 15)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.476261
This article presents the design of a VLSI fuzzy processor which is capable of performing fuzzy inferences. An analysis of inference methods and their computational complexity has led to the definition of an inference technique which optimizes processing times. The results of this analysis also dictated our choice of the architecture for the processor. The main features of the architecture are: pre-processing of inferences to reduce the number of rules to be processed; parallel computation of the degree of activation of the active rules and scalability. The performance obtainable is in the order of 320KFLIPS (256 rule, 8 inputs, 2 output).
Fuzzy hardware, VLSI, processors, parallel computation
Vincenzo Catania, Marco Russo, Biagio Giacalone, Lorenzo Vita, Giuseppe Ascia, "Designing for Parallel Fuzzy Computing", IEEE Micro, vol. 15, no. , pp. W1-W11, December 1995, doi:10.1109/40.476261