Issue No. 02 - April (1995 vol. 15)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.372352
The PowerPC architecture permits aggressive hardware and software implementations that improve performance by hiding the large relative latency of memory accesses. Hardware and software cooperatively determine the behavior of the memory system, using the architecture's provisions for atomicity, coherence, and synchronization of accesses. The design philosophy is to streamline interfaces among components, to limit synchronization delays. For the memory system, the problem is to reduce processor delays during memory accesses. This motivated the development of systems in which useful work can be accomplished during latency periods. While the processor awaits the arrival of a datum, it can often fetch other data, do computations that do not require the awaited datum, and store other data. Such reordering is limited by data dependences among accesses and computation.
PowerPC, storage, microprocessor latency
Robert P. Fitzgerald, Janice M. Stone, "Storage in the PowerPC", IEEE Micro, vol. 15, no. , pp. 50-58, April 1995, doi:10.1109/40.372352