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ABSTRACT
The design of a single chip PowerPC Reference Platform Specification compliant bridge between a PowerPC microprocessor and the PCI bus is described. The MPC105 PCI Bridge/Memory Controller allows system designers to rapidly design systems using peripherals already designed for PCI and the other standard interfaces available in the personal computer hardware environment. The MPC105 also integrates a secondary cache controller and a high performance memory controller which supports DRAM or SDRAM and ROM or Flash ROM. This article highlights the design features and discusses the architecture, performance, package technology, power management, and physical implementation.
INDEX TERMS
microprocessors, PowerPC, PCI bus, memory controllers
CITATION
Glen Wilson, Karl Wang, Adrian Harris, Laura Weber, C. K. Leung, Michael Garcia, C. S. Hui, Chris Bryant, Jim Wenzel, Mike Carlson, Mike Elmer, Mike Becker, Brian Reynolds, Raymond Tang, "Designing the MPC105 PCI Bridge/Memory Controller", IEEE Micro, vol. 15, no. , pp. 44-49, April 1995, doi:10.1109/40.372351
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