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Issue No.03 - June (1994 vol.14)
pp: 51-59
<p>Developed for the VLSI implementation of neural network models, our novel analog architecture adds flexibility and adaptability by incorporating digital processing capabilities. Its systolic-based architecture avoids static storage of analog values by transferring the activation values through the chip's processing units. This proposed combination of analog and digital technologies produces a densely packed, high-speed, scalable architecture, designed to easily accommodate learning capabilities.</p>
Juan M. Moreno, Francisco Castillo, Joan Cabestany, Jordi Madrenas, Andrezj Napieralski, "An Analog Systolic Neural Processing Architecture", IEEE Micro, vol.14, no. 3, pp. 51-59, June 1994, doi:10.1109/40.285224
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