Issue No. 03 - June (1994 vol. 14)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.285224
<p>Developed for the VLSI implementation of neural network models, our novel analog architecture adds flexibility and adaptability by incorporating digital processing capabilities. Its systolic-based architecture avoids static storage of analog values by transferring the activation values through the chip's processing units. This proposed combination of analog and digital technologies produces a densely packed, high-speed, scalable architecture, designed to easily accommodate learning capabilities.</p>
J. Madrenas, F. Castillo, A. Napieralski, J. Cabestany and J. M. Moreno, "An Analog Systolic Neural Processing Architecture," in IEEE Micro, vol. 14, no. , pp. 51-59, 1994.