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Issue No.05 - September/October (1992 vol.12)
pp: 28-32
<p>The architecture and characteristics of a fully functional 40 MHz device that performs the 8*8 inverse discrete cosine transform (IDCT) for digital HDTV decoders are presented. The IDCT chip converts four 14-b DCT coefficients into four 11-b pixel values each cycle. Fixed-coefficient multiplier Wallace trees in which partial products are rounded before summation help compute the inner products. The 31000-gate device was implemented in a 10.5 mm die using 1 mu m CMOS array-based process.</p>
Peter A. Ruetz, Po Tong, "A 160 Mpixel/s IDCT Processor for HDTV", IEEE Micro, vol.12, no. 5, pp. 28-32, September/October 1992, doi:10.1109/40.166710
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