Issue No. 05 - September/October (1992 vol. 12)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.166710
<p>The architecture and characteristics of a fully functional 40 MHz device that performs the 8*8 inverse discrete cosine transform (IDCT) for digital HDTV decoders are presented. The IDCT chip converts four 14-b DCT coefficients into four 11-b pixel values each cycle. Fixed-coefficient multiplier Wallace trees in which partial products are rounded before summation help compute the inner products. The 31000-gate device was implemented in a 10.5 mm die using 1 mu m CMOS array-based process.</p>
P. A. Ruetz and P. Tong, "A 160 Mpixel/s IDCT Processor for HDTV," in IEEE Micro, vol. 12, no. , pp. 28-32, 1992.