The Community for Technology Leaders
Green Image
<p>The heterogeneous vision architecture that satisfies the computing demands of real-time computer vision by providing parallelism in three different forms is described. A pipeline of digital signal processing (DSP) chips initially processes signals. Then a SIMD associative processor array processes images and extract features, and a MIMD network of transputers processes extracted objects in parallel. The array's VLSI implementation, the processing modes available due to the use of content-addressable memory, and the means of achieving efficient 2-D interprocessor communication in the linear array are described. An application as a vehicle number plate recognition system is presented.</p>
Andrew W.G. Duller, Peter J. Hick, Erik L. Dagless, Andrew R. Thomson, Richard Storer, Mike R. Pout, A. Paul Marriott, "An Associative Processing Module for a Heterogeneous Vision Architecture", IEEE Micro, vol. 12, no. , pp. 42-55, May/June 1992, doi:10.1109/40.141602
98 ms
(Ver 3.1 (10032016))