Issue No. 05 - September/October (1990 vol. 10)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.60527
<p>Theoretical aspects of encoding cyclic redundant codes (CRCs) are reviewed. A method of designing hardware parallel encoders for CRCs that is based on digital system theory and z-transforms is presented. It allows designers to derive the logic equations of the parallel encoder circuit for any generator polynomial. A few interesting application areas for hardware parallel encoders are pointed out.</p>
R. Sisto and G. Albertengo, "Parallel CRC Generation," in IEEE Micro, vol. 10, no. , pp. 63-71, 1990.