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<p> The design of the 68040, a third-generation, full-32-b microprocessor in the Motorola 68000 family, is presented. The 68040 integrates over 1.2 million transistors on one chip and can execute the complete 68020 microprocessor and 68882 floating-point coprocessor instruction sets. Pipelined integer and floating-point execution units that operate concurrently with separate internal memory controllers and an autonomous bus controller contribute to its high performance level. Physical caches of 4 kB each for instruction and data reside on chip. Separate address-translation caches of 64 entries apiece operate in parallel with the instruction and data caches. This arrangement provides complete memory management in a virtual, demand-paged operating system. The design team explains its total approach and the workings of the integer and floating-point units.</p>

W. B. Ledbetter, Jr., R. C. McGarity, E. E. Quintana, M. G. Gallup, R. W. Edenfield and R. A. Reininger, "The 68040 Processor. I. Design and Implementation," in IEEE Micro, vol. 10, no. , pp. 66-78, 1990.
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