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<p>A joint development project that implemented Sun Microsystems' scalable processor architecture (Sparc) with Bipolar Integrated Technology's bipolar emitter-coupled logic (ECL) is described. The authors review both ECL technology and the features of BIT's ECL technique and discuss how board and cache considerations influenced the chip designs. Also discussed are the integer unit pipeline, system interface signals, and coprocessor interface. The chip set, now completed, performs at a level equal to large mainframe computers and approaches that of today's supercomputers.</p>

D. Murata, M. F. Klein, T. Creary, J. Petolino, E. W. Brown and A. Agrawal, "Implementing Sparc in ECL," in IEEE Micro, vol. 10, no. , pp. 10-22, 1990.
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