Issue No. 06 - November/December (1989 vol. 9)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.42987
<p>An associative memory circuit that may let designers expand neural networks around a matrix of analog synapses is described. The architecture of the chip and its basic cell are discussed, and some SPICE simulation results are presented and compared with measures provided by the first prototype. In particular, the linearity and dynamic response of the complete chip, which includes an array of 25 synapses and two address decoders used for programming the weights, are examined.</p>
O. Rossetto, I. Kreuzer, J. Herault and C. Jutten, "Analog VLSI Synaptic Matrices as Building Blocks for Neural Networks," in IEEE Micro, vol. 9, no. , pp. 56-63, 1989.