Issue No. 06 - November/December (1989 vol. 9)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.42986
<p>The basic requirements for electronic implementations of the fully connected Hopfield network are examined, highlighting the reasons why the authors regard analog implementations as more appropriate. Analog VLSI networks are then discussed, with particular reference to the selection of memory points and the design of the synapse, and experimental results are given. A test chip containing 14 neurons and 196 synapses is described.</p>
M. Verleysen and P. G. Jespers, "An Analog VLSI Implementation of Hopfield's Neural Network," in IEEE Micro, vol. 9, no. , pp. 46-55, 1989.