A Floating-Point VLSI Chip for the TRON Architecture: An Architecture for Reliable Numerical Programming
Issue No. 03 - May/June (1989 vol. 9)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.31476
<p>A description is given of the Gmicro/FPU (floating-point unit), a chip that provides floating-point instructions for both the Gmicro/200 and the Gmicro/300 microprocessors. The VLSI central-processing-unit architecture, for which it is designed, defines 23 coprocessor instructions, some of which are designed to be used in the floating-point instructions. Some background information is given, and the requirements, architecture, implementation, and evaluation of the Gmicro/FPU are discussed.</p>
M. Watabe, S. Morinaga and S. Kawasaki, "A Floating-Point VLSI Chip for the TRON Architecture: An Architecture for Reliable Numerical Programming," in IEEE Micro, vol. 9, no. , pp. 26-44, 1989.