Issue No. 05 - September/October (1988 vol. 8)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.87518
<p>The author presents ASP architecture, which offers cost-effective support of a wide range of numerical and nonnumerical computing applications, using state-of-the-art microelectronic technology to achieve processor packing densities that are more usually associated with memory components, ASP is designed to benefit from the inevitable VLSI-to-ULSI-to-WSI (very large, ultra large, and wafer-scale integration) technological trend, with a fully integrated, simply scalable, and defect/fault-tolerant processor interconnection strategy. The author discusses the architectural philosophy, structural organization, operational principles, and VLSI/ULSI/WSI implementation of ASP and indicates its cost-performance potential. ASP microcomputers have the potential to achieve cost-performance targets in the range of 100 to 1000 MOPS (million operations per second) per $1000. This gives ASPs an advantage of two to three orders of magnitude over current parallel computer architectures.</p>
R. Lea, "ASP: A Cost-Effective Parallel Microcomputer," in IEEE Micro, vol. 8, no. , pp. 10-29, 1988.