Issue No. 03 - May/June (1988 vol. 8)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.542
<p>Two options are presented that were considered for a pipelined interface between a central processing unit (CPU) and a floating-point coprocessor (FPU), along with the CPU recovery mechanisms that provide precise floating-point exceptions for each option. The first option supports parallel execution of both floating-point and integer instructions, while the second option pipelines only the execution of floating-point instructions. The use of the second option in National Semiconductor's 32532/32580 processor cluster because it offers high performance with significantly lower complexity. The 32532 microprocessor features a pipelined slave protocol that hides the CPU-FPU communication overhead for most floating-point instructions by pipelining their execution. A simple recovery mechanism implemented within the CPU maintains the precision of floating-point exceptions. As a result, the 32532 microprocessor supports very high floating point performance without sacrificing software compatibility with previous Series 32000 CPU-FPU clusters.</p>
S. Iacobovici, "A Pipelined Interface for High Floating-Point Performance with Precise Exceptions," in IEEE Micro, vol. 8, no. , pp. 77-87, 1988.