Issue No. 03 - May/June (1988 vol. 8)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.541
<p>Important features and capabilities of the 80960 are briefly examined, and an overview of its architecture is given. A detached discussion is presented of the register model, core instruction set, register operations, memory operations, control operations instruction cache, user-supervisor protection, interrupts, faults, and debug support.</p>
D. P. Ryan, "Intel's 80960: An Architecture Optimized for Embedded Control," in IEEE Micro, vol. 8, no. , pp. 63-76, 1988.