Issue No. 03 - May/June (1988 vol. 8)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.540
<p>A description is given of the R3010 floating-point accelerator chip, a coprocessor that is based on advanced reduced-instruction-set-computer (RISC) architecture and VLSI design techniques and provides high-speed floating-point operation. The 75000-transistor hard-wired chip executes four instructions in parallel. Its performance is compared with that of available floating-point processors and its architecture is examined. The organization and implementation of the R3010 is discussed.</p>
C. Rowen, P. Ries and M. Johnson, "The MIPS R3010 Floating-Point Coprocessor," in IEEE Micro, vol. 8, no. , pp. 53-62, 1988.