Issue No. 02 - March/April (1988 vol. 8)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.528
<p> The 32-bit TX1 microprocessor, developed to meet the architectural specification of Japan's TRON (The Real-Time-Operating Nucleus) project, has been given a loosely coupled pipeline structure to meet the demands of high-performance systems. The authors discuss the design architecture of the TX1, provide some performance analysis for the design, and describe the debugging feature provided on the processor. Results for several benchmark programs show that the average performance of the TX1 is over 5 MIPS (million instructions per second).</p>
H. Kishigami, S. Kamiya, M. Miyata and K. Okamoto, "The TX1 32-Bit Microprocessor: Performance Analysis, and Debugging Support," in IEEE Micro, vol. 8, no. , pp. 37-46, 1988.