Issue No. 02 - March/April (1988 vol. 8)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.526
<p> The Gmicro/200, a microprocessor that has been developed as part of Japan's TRON (The Real-Time Operating Nucleus) project, is described. This microprogram-based processor with six-state pipeline, 730000 transistors and on-chip caches will serve in an engineering workstation or a high-speed graphics accelerator system. The authors discuss features of the instruction set; memory management; handling of exceptions, interrupts and traps; and the implementation of the Gmicro/200.</p>
I. Kawasaki, K. Sakamura, H. Inayoshi and T. Nishimukai, "Realization of Gmicro/200," in IEEE Micro, vol. 8, no. , pp. 12-21, 1988.