Issue No. 02 - March/April (1986 vol. 6)
Brad Cohen , Motorola Microprocessor Products Division
Ralph McGarity , Motorola Microprocessor Products Division
Pipelining, microsequencer start-up in parallel with bus arbitration, and a fully associative translation cache enhanced the performance of this 32-bit memory management device.
R. McGarity and B. Cohen, "The Design And Implementation of the MC68851 Paged Memory Management Unit," in IEEE Micro, vol. 6, no. , pp. 13-28, 1986.