DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2011.70
Seetharam Narasimhan , Case Western Reserve University, Cleveland
Rajat Chakraborty , Indian Institute of Technology, Kharagpur, Kharagpur
Swarup Bhunia , Case Western Reserve University, Cleveland
Evaluation of hardware Intellectual Property (IP) cores is an important step in an IP-based system-on-chip (SoC) design flow. From the perspective of both IP vendors and Integrated Circuit (IC) designers, it is desirable that hardware IPs can be freely evaluated before purchase, similar to their software counterparts. However, protection of these IPs against piracy during evaluation is a major concern for the IP vendors. Existing solutions typically use encryption and vendor-specific toolsets, which may be unacceptable due to lack of flexibility to use in-house or third-party design tools. We propose a novel low-cost solution for hardware IP protection during evaluation, by embedding a hardware Trojan inside an IP in the form of a finite state machine (FSM) with special structure. The Trojan disrupts the normal functional behavior of the IP on occurrence of a sequence of rare events, thereby effectively putting an “expiry date” on the usage of the IP. The Trojan is structurally and functionally obfuscated, thus protecting against potential reverse engineering efforts that target isolation of the Trojan circuit.
B.1.m.a Emerging technologies, B.9.1 Low-power design, B.0 General, B.4.5 Reliability, Testing, and Fault-Tolerance, BIST, yield, robust design, process variations, nano architecture, low power, B Hardware, B.6.2 Reliability and Testing, BIST, Yield, Self-Testing, Profit, Manufacturing Cost, Fault Tolerance, delay testing, B.0 General, B.5.0 General, K.4.4.d Intellectual property, K.5.1 Hardware/Software Protection, K.6.5 Security and Protection, K.6.m.b Security
S. Bhunia, S. Narasimhan and R. Chakraborty, "Hardware IP Protection During Evaluation Using Embedded Sequential Trojan," in IEEE Design & Test of Computers.