V. Rana , V. Rana is with Embedded Systems Laboratory (ESL), EPFL, Lausanne, 1015, Switzerland.(email:email@example.com)
Traditionally, parallel implementations of multimedia algorithms are carried out manually, since the automation of this task is very difficult due to the complex dependencies that generally exist between different elements of the data set. Moreover, there is a wide family of iterative multimedia algorithms that cannot be executed with satisfactory performance on Multi-Processor Systems-on-Chip or Graphics Processing Units. For this reason, new methods to design custom hardware circuits that exploit the intrinsic parallelism of multimedia algorithms are needed. As a consequence, in this paper, we propose a novel design method for the definition of hardware systems optimized for a particular class of multimedia iterative algorithms. We have successfully applied the proposed approach to several realworld case studies, such as iterative convolution filters and the Chambolle algorithm, and the proposed design method has been able to automatically implement, for each one of them, a parallel architecture able to meet real-time performance (up to 72 frames per second for the Chambolle algorithm), with on-chip memory requirements from 2 to 3 orders of magnitude smaller than the state-of-the art approaches.
M. Santambrogio, A. Nacci, I. Beretta, D. Sciuto, D. Atienza and V. Rana, "Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms," in IEEE Design & Test of Computers.