The Community for Technology Leaders
Green Image
ISSN: 0740-7475
Samah Saeed , Samah Mohamed Saeed is with the Computer Engineering Department Institute of Technology University of Washington - Tacoma. (email: samahsaeed88@hotmail.com)
ABSTRACT
While both testability and security of Integrated Circuits (ICs) are of major concern, they seem to be two conflicting goals. The former one aims at reaching deep inside the IC to expose defects, while the latter one aims at hiding and protecting secret information of the IC. In this paper, we first present various cost-effective and orthogonal Design-for-Testability (DfT) techniques improving various aspects of test, while pointing out the security vulnerability induced by any state-of-the-art DfT infrastructure. We then show that both testability and security can be delivered in an orthogonal manner, leading to the development of testable yet secure designs.
INDEX TERMS
Testing, Security, Integrated circuits, Compaction, Registers, Circuit faults, Observability
CITATION

S. Saeed and O. Sinanoglu, "A Comprehensive Design-for-Test Infrastructure In the Context of Security-Critical Applications," in IEEE Design & Test of Computers.
doi:10.1109/MDAT.2016.2527708
95 ms
(Ver 3.3 (11022016))