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Pre-bond testing of silicon interposers is difficult due to the large number of nets to be tested and the small number of test access ports. To solve the problem, we propose to include a test interposer that is contacted with the interposer under test in the testing process. Combining these two interposers provides access to nets that are not normally accessible. A study on how to synthesize testable interconnect structure is presented. Based on the analysis, an efficient synthesis method is developed. In this approach, a single test interposer can be used for both open and short fault detection, which leads to shorter test time and lower test cost.
Circuit faults, Testing, Silicon, Wires, Three-dimensional displays, Through-silicon vias, Stacking

K. S. Li, S. Wang, R. Ku and B. Chen, "Pre-bond Test of Silicon Interposer with Test Interposer," in IEEE Design & Test of Computers.
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