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Issue No.06 - December (2013 vol.30)
pp: 70-79
ABSTRACT
The number of open defects in vias has increased with the introduction of the copper process, smaller geometries, and via counts in the order of billions for modern integrated circuits. The authors investigate reliability risks by estimating the Median Time to Failure (MTF) as a function of the void size in vias placed. The number of open defects in vias has increased with the introduction of the copper process, smaller geometries, and via counts in the order of billions for modern integrated circuits. The authors investigate reliability risks by estimating the Median Time to Failure (MTF) as a function of the void size in vias placed on signal paths.
INDEX TERMS
Current density, Reliability, Nanoscale devices, Electromigration, Resistance, Failure analysis,Resistive Opens, Small Delay Defect, Via Reliability, Electromigration, Blacks Law, Via Duplication
CITATION
"Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths", IEEE Design & Test of Computers, vol.30, no. 6, pp. 70-79, December 2013, doi:10.1109/MDT.2013.2238578
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