The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.04 - August (2013 vol.30)
pp: 60-70
ABSTRACT
In this contribution, the authors describe a method for ensuring that false failures do not occur when shifting scan chains for testing. Their approach identifies an optimal combination of scan segments for simultaneous clocking that reduces the switching activity near clock trees while maintaining the average power reduction for conventional scan segmentation. Experiments using various benchmark circuits demonstrate the overall utility of their approach.
INDEX TERMS
Timing analysis, Synchronization, Clocks, Logic gates, Power consumption, Failure analysis, Software testing,clock skew, scan testing, shift power reduction, scan segmentation, switching activity, clock tree
CITATION
"LCTI–SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing", IEEE Design & Test of Computers, vol.30, no. 4, pp. 60-70, August 2013, doi:10.1109/MDT.2012.2221152
SEARCH
4 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool