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In this contribution, the authors describe a method for ensuring that false failures do not occur when shifting scan chains for testing. Their approach identifies an optimal combination of scan segments for simultaneous clocking that reduces the switching activity near clock trees while maintaining the average power reduction for conventional scan segmentation. Experiments using various benchmark circuits demonstrate the overall utility of their approach.
Timing analysis, Synchronization, Clocks, Logic gates, Power consumption, Failure analysis, Software testing,clock skew, scan testing, shift power reduction, scan segmentation, switching activity, clock tree
"LCTI–SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing", IEEE Design & Test of Computers, vol. 30, no. , pp. 60-70, August 2013, doi:10.1109/MDT.2012.2221152
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