Issue No.04 - August (2013 vol.30)
In this paper, we propose an approach to generate high-level test patterns from the arithmetic model of a register-transfer-level (RTL) circuit using a hybrid canonical data structure based on a decision diagram. High-level simplified and fast symbolic path activation strategy as well as input justification is combined with test pattern generation for circuits under consideration. The current approach has been implemented for a range of small to large benchmark circuits. The results clearly demonstrate that tests generated using the proposed method have achieved high fault coverage for known sequential circuit benchmarks in very short central processing unit (CPU) time and minimum memory usage.
Circuit faults, Polynomials, Integrated circuit modeling, Logic gates, Encoding, Automatic test pattern generation,RTL Circuits, Automatic Testin, Canonical Representation, Test Pattern Generation
"A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits", IEEE Design & Test of Computers, vol.30, no. 4, pp. 49-59, August 2013, doi:10.1109/MDT.2012.2217471