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Issue No. 02 - April (2013 vol. 30)
ISSN: 0740-7475
pp: 35-44
J. Rajendran , Polytech. Inst., New York Univ., New York, OH, USA
A. K. Kanuparthi , Polytech. Inst., New York Univ., New York, NY, USA
M. Zahran , New York Univ., New York, NY, USA
S. K. Addepalli , Cisco, USA
G. Ormazabal , Columbia Univ., New York, NY, USA
R. Karri , Polytech. Inst., New York Univ., New York, OH, USA
Modification to traditional SoC design flow can enable effective protection against maliciously inserted rogue functionality during design and fabrication. This article presents a joint circuit-architecture-level design approach that helps in preventing or detecting Trojan attacks.
system-on-chip, network synthesis, security, Trojan attack detection, processor, insider attack, circuit microarchitecture codesign approach, modification, SoC design flow, rogue functionality, fabrication, circuit architecture level design, Trojan horses, Program processors, Logic gates, Encryption, Computer security, Hardware, Computer architecture, Hardware security, Hardware-based insider attacks, Logic encryption, Circuit micro-architecture co-design

J. Rajendran, A. K. Kanuparthi, M. Zahran, S. K. Addepalli, G. Ormazabal and R. Karri, "Securing Processors Against Insider Attacks: A Circuit-Microarchitecture Co-Design Approach," in IEEE Design & Test of Computers, vol. 30, no. , pp. 35-44, 2013.
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