Pages: pp. 92-93
Abstract—This newsletter provides information on past and upcoming events related to the IEEE Computer Society's Test Technology Technical Council and the test community.
Keywords—design and test, TTTC, test technology, ITC, ATS, IDT, DFT
18–23 September 2011
The 42nd International Test Conference was held at the Disneyland Hotel in Anaheim, California, 18–23 Sept. It focused on leading-edge solutions and the latest thinking in the electronics test technology industry. Sponsored by the IEEE Philadelphia Section and the IEEE Computer Society, and in alliance with the Global Semiconductor Alliance, ITC highlights advances and emerging technologies that address the practical challenges of the test industry.
On 18 and 19 September, Test Week opened with 12 full-day tutorials covering diverse topics taught by experts from both industry and academia. The formal technical program featured 76 presentations covering 10 different topic areas, as well as offering daily panel sessions and a lunchtime poster session. Topics such as test compression, power-aware test, delay test, logic diagnosis, postsilicon debug, and test-data mining were addressed. Hot topics that included the test of through-silicon vias (TSVs) and high-speed I/O were also part of the program. The popular and successful poster session included tabletop displays that allowed attendees and presenters to easily engage on the late-breaking results and innovative methods presented. Rounding out Test Week were three lauded and well-attended IEEE workshops held on 3D test, silicon debug and diagnosis, and adaptive test.
The conference featured opening and closing keynotes. On Tuesday, 20 Sept., Bill Dally (Bell Professor of Engineering, Stanford University, and Chief Scientist, Nvidia) presented an interesting look into the future of computing. On Thursday, 22 Sept., Jyuo-Min Shyu (president, Industrial Technology Research Institute [ITRI], Taiwan) looked at the process of translating scientific discoveries into processes and tools that provide significant business value.
A fascinating invited talk also took place on Wednesday, 21 Sept., when Chuck Davis, a Disney Imagineer, explained the technology behind the creation of Disney's spectacular show World of Color.
3–5 October 2011
The annual DTF in VLSI and Nanotechnology Systems symposium provides an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, both necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest. This year, the symposium was held in Vancouver, British Columbia, Canada.
The DFT program consisted of 15 regular sessions, one poster session, and three keynote presentations. Keynote presenters were N. Seifert (Intel), Lorena Anghel (TIMA Labs), and Said Hamdioui (Delft University of Technology).
21–23 November 2011
New Delhi, India
The Asian Test Symposium 2011 is the 20th in this series of symposia begun in 1992 and devoted to testing, fault-tolerant computing, and the design of reliable circuits and systems. ATS is recognized as the main event in Asia that covers the many dimensions of testing and fault tolerance. In 2011, the 20th anniversary of the Asian Test Symposium will be celebrated in New Delhi, India, and is of particular significance due to the rise of Asia, over the past several decades, in the areas of integrated circuit design and manufacturing, and electronic systems and software engineering, both of which embrace testing as a core technology.
The theme for ATS 2011 will be "Test Odyssey 2020: Testing Systems and Devices at the Peta and Nano Scales." This theme is inspired by the fact that technology is trending toward extremely high levels of integration at the package and chip levels, very high speeds of operation (greater than 100 GHz) and use of deeply scaled technology (approaching 10-nm CMOS process). In addition, it will be a key test challenge to address the complexity that will result from the ability to design intricate systems— such as robots—that encompass sensors, communications systems, processors, transducers, and enabling software. In addition to passing postmanufacture test procedures, such systems and relevant devices must exhibit fault tolerance and survivability characteristics.
A special event will be the Asian Semi-Final of the TTTC's E.J. McCluskey Doctoral Thesis Award (doctoral student contest) that will be held in conjunction with ATS 2011. The winner will be determined by the industrial jury and the academic jury. The winner will compete against other regional winners at the International Test Symposium 2012 finals.
11–14 December 2011
The International Design and Test Conference provides a unique forum to discuss novel approaches in design, automation, and test in the Middle East and Africa (MEA) region for researchers and practitioners in the areas of VLSI design, test, and fault tolerance to come together to discuss new research ideas and present new research results. This event will provide the only VLSI design-and-test-specific meeting in the MEA region. In addition to traditional research papers, IDT will also have hot topic sessions and panel discussions. IDT will be colocated with the IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2011), the flagship conference of the IEEE CAS Society.
I would appreciate input and suggestions about the newsletter from the test community. Please forward your ideas, contributions, and information on awards, conferences, and workshops to Partha Pande, School of Electrical Engineering and Computer Science, Washington State University, PO Box 642752, Pullman, WA 99164-2752; email@example.com.
Editor, TTTC Newsletter
For more details and free membership, browse the TTTC Web page: http://tab.computer.org/tttc.