Issue No. 06 - Nov.-Dec. (2011 vol. 28)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2011.24
Youngsoo Shin , KAIST
Seungwhun Paik , Synopsys
<p>Pulsed-latch circuits retain the advantages of both latches and flip-flops, offering higher performance and lower power consumption within a conventional ASIC design environment. This article identifies a design methodology and tools for pulsed-latch ASICs to complement this environment. The authors review potential solutions and provide quantitative results to assess the effectiveness of pulsed-latch circuits.</p>
design and test, pulsed latch, pulsed-latch ASIC methodology, high performance, low power
Y. Shin and S. Paik, "Pulsed-Latch Circuits: A New Dimension in ASIC Design," in IEEE Design & Test of Computers, vol. 28, no. , pp. 50-57, 2011.