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Issue No.05 - September/October (2011 vol.28)
pp: 36-51
Peter A. Beerel , University of Southern California and Fulcrum Microsystems
Georgios D. Dimou , Fulcrum Microsystems
Andrew M. Lines , Fulcrum Microsystems
<p>Editors' note:</p><p>The high-performance benefits of asynchronous design have hitherto been obtained only using full-custom design. This article presents an industrial-strength asynchronous ASIC CAD flow that enables the automatic synthesis and physical design of high-level specifications into GHz silicon, greatly reducing design time and enabling far wider use of asynchronous technology.</p><p align="right">&#x2014;Montek Singh (UNC Chapel Hill) and Luciano Lavagno (Politecnico di Torino)</p>
design and test, asynchronous design, high performance, slack matching, communicating sequential processes, asynchronous place and route
Peter A. Beerel, Georgios D. Dimou, Andrew M. Lines, "Proteus: An ASIC Flow for GHz Asynchronous Designs", IEEE Design & Test of Computers, vol.28, no. 5, pp. 36-51, September/October 2011, doi:10.1109/MDT.2011.114
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