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Test Technology TC Newsletter

Pages: pp. 108-109

Abstract—This newsletter provides information on past and upcoming events related to the IEEE Computer Society's Test Technology Technical Council and the test community.

Keywords—design and test, TTTC, test technology, ITC, ETS, ATS, DFT


29th VLSI Test Symposium (VTS 2011)

1–5 May 2011

Dana Point, California

The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in testing, and verification and validation, of microelectronic circuits and systems. The VTS 2011 program featured several traditional sessions with paper presentations; the program also included special and IP (innovative practice) sessions. The keynote address, delivered by Sanjiv Taneja (Cadence Design Systems), was "Cost-Effective Innovation to Address Next-Generation Challenges in Design and Test." Additionally, two invited keynote talks were delivered by Fadi Kurdahi (University of California, Irvine) and Michael Nicolaidis (TIMA).

As part of VTS 2011, the Test Technology Technical Council's E.J. McCluskey Best Doctoral Thesis 2011 Award contest was held. The McCluskey award contest consists of three semifinal events: The first was held at the IEEE Asian Test Symposium (ATS 2010); the second was at VTS 2011, and the third was held at the IEEE European Test Symposium (ETS 2011); the winner is to be announced at ITC 2011. The contest provides graduate students with an opportunity to disseminate their research, obtain visibility in the international test community, and achieve recognition for their achievements.

16th IEEE European Test Symposium (ETS 2011)

23–27 May 2011

Trondheim, Norway shtml

The European Test Symposium is Europe's premier forum dedicated to presenting and discussing scientific results, emerging ideas, practical applications, hot topics, and new trends in the area of electronic-based circuit and system testing. The 16th edition of ETS, which continued its well-established format with a three-day technical program, also offered an attractive social event. The symposium's technical program consisted of two plenary keynote addresses, technical paper presentations in three parallel sessions, two embedded tutorials, three poster sessions, two panels, and a special session featuring a student contest and student work-in-progress presentations. Several test-related fringe (ancillary) events completed the European Test Week. These events included the 4th IEEE International Workshop on the Impact of Low Power Design on Test and Reliability (LPonTR 2011), the IEEE International Workshop on Processor Verification, Test and Debug (IWPVTD 2011), the Test Spring School, and the first Workshop on Dependability Issues in Deep-submicron Technologies (DDT).

ETS 2011 received a large number of contributions from all over the world, submitted to the scientific track, workshop track (including emerging ideas and case studies), vendor sessions, and special sessions. Based on the reviews and the discussions, 32 scientific track papers—and 18 one-page abstracts describing corresponding posters—were selected for inclusion in the symposium's published formal proceedings. In addition, 10 contributions for the workshop track and 12 vendor session presentations were selected; most had corresponding papers in the informal part of the electronic proceedings.


IEEE International Test Conference (ITC 2011)

18–23 September 2011

Anaheim, California

The International Test Conference, cornerstone of Test Week events, is the world's premier conference devoted to the electronic test of devices, boards, and systems—covering the complete cycle from design verification, test, diagnosis, failure analysis, and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers. To encourage excellence in its technical program, ITC will present awards to authors of outstanding papers. In determining award-winning papers, the ITC Awards Selection Committee considers the quality of the papers as published in the proceedings and as presented at the conference technical sessions. The committee's decisions are based on responses from conference attendees as recorded on session rating cards and on the observations and recommendations of the ITC Program Committee.

The final competition for TTTC's E.J. McCluskey Best Doctoral Thesis 2011 Award will be held at ITC 2011. The winners from the semifinal events at ATS 2010, VTS 2011, and ETS 2011 will compete for the final award.

IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2011)

3–5 October 2011

Vancouver, Canada

DFT is an annual symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems, including emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, both of which are necessary ingredients for significant advances in this field. Of interest are all aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation.

The DFT symposium will be held this year in Vancouver, British Columbia, Canada. Papers will be accepted for regular or poster presentation at the symposium. Proceedings will be published by the IEEE Computer Society and will be included in the IEEE Digital Library. All papers with a student as both primary author and presenter will be considered for the 2011 Best Student Paper Award, sponsored by Intel. Authors will have the opportunity to submit an extended version of their paper presented at the symposium in a special issue of an archival journal.

Newsletter Editor's Invitation

I would appreciate input and suggestions about the newsletter from the test community. Please forward your ideas, contributions, and information on awards, conferences, and workshops to Partha Pande, School of Electrical Engineering and Computer Science, Washington State University, PO Box 642752, Pullman, WA 99164-2752;

Partha Pande

Editor, TTTC Newsletter

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